Research in the MSDA Lab

The Mixed - Signal Design Automation (MSDA) Lab at SJTU has been working on several research projects centered around the traditional mixed - signal CMOS circuit design technology and some emerging directions driven by programmable nonvolatile devices (such as memristor). The MSDA Lab places its research emphasis mainly on design automation technologies that have underdeveloped (for example analytical approaches). We have dedicated a great amount of research effort to the design automation of analog ICs via analytical approach, the AICE tool is an outcome of this effort.

We have also developed recently a SPICE simulator capable of memristor simulation by extending the open source NGSPICE available in sourceforge. We have made this extension Memr-SPICE open source in hope of sharing knowledge to the community and improving research on memristor-based circuits and systems.

• Li, Bo (since 2015)
• Xie, Qixu (since 2016)
• Hao, Limin (since 2018)
• Deng, Qiyu (since 2020)
• Li, Mingzhen (since 2021)

• Hao, Zhigang (defense completed 2012)
• Zhang, Ailin (defense completed 2020)

For consulting opportunities to study in the MSDA Lab, please contact Prof. Guoyong Shi (shiguoyong@sjtu.edu.cn). Prospective students should have strong background in the following aspects:

• Proficiency in programming (C++ preferred, knowledge on Qt is a plus)
• Working knowledge in CMOS analog IC
• Good standing in mathematics and algorithms
• Self-motivated working habits

AICE – Analog IC Explorer

AICE is a symbolic circuit analysis program which was developed to help analog IC designers do fast analysis work. If designers would like to acquire insight on a conceptual design, like the transfer functions (TFs) of a conceptual schematic, poles and zeros (PZs), the effect of compensations, and the effect of load, and other analytical design equations, etc., AICE is a CAD tool for these. The key feature of AICE is its capability to generate analytical results instantaneously, support instant simplification, and offer (in the future) computer algebra support, all fast and intuitive enough so that designers can quickly explore design space by saving pencil-and-paper time.

AICE was designed to generate readable symbolic results by its build-in computer algebra engine. We recommend users to use it for analyzing conceptual circuits rather than full transistor-level circuits. If the circuit scale is too large (involving too many parasitics), the generated results would not be friendly for reading. Recently we have developed another feature that can help the user reduce a transistor-level circuit to stage form macromodels automatically. This feature can further help designers to generate design equations and use them to modify compensation in opamps and device sizing.

The philosophy of developing a tool like AICE is noticing that analog IC design is mainly a reasoning process, and more importantly this reasoning is not like mathematics where everything is exact, rather it is “approximate”. Approximate reasoning constitutes the key means of innovation in analog IC. Designers have to fully exercise their well-trained approximation abilities to find simplified circuit level representations, design equations, conceptual circuit blocks, etc. to facilitate reasoning. This kind of design practice makes the synthesis process of analog IC (if anybody is thinking on its automation) completely different from other parts of design automation like digital IC.

A more detailed discussion on the notion of “approximate inference/reasoning” in analog IC please refer to (Shi, Integration the VLSI Journal, 2018). If approximate reasoning is a key issue, symbolic circuit analysis must receive more attention than it ought to be because in my personal opinion this discipline has not received adequate research attention in the academia and most of prior research efforts either failed to discover groundbreaking principles or pursued many misleading directions. For example, using numerical reference as a guide to simplify symbolic expressions is a completely wrong strategy. In the recent publications listed below we have been striving to offer new contributions to fill a number of blanks. Symbolic computation is currently the only available avenue to automation tools capable of approximate reasoning.

The symbolic analysis engine behind AICE is the GPDD (graph-pair decision diagram) algorithm originally proposed by (Shi, TCAD, 2013). A more thorough exposition on this algorithm is presented in the book (Shi, Tan, and Tlelo-Cuautle, Springer, 2014). In principle, this symbolic method can be applied to both large and small-scale analog circuits. For large-scale analog circuit the generated symbolic results could be too lengthy to be readable. Hence, it should not be considered the main usefulness of symbolic analysis.

On the contrary, on many occasions analog designers would like to view the symbolic results generated by a tool. For that purpose, either the schematic entered for analysis should be kept small or the tool should be able to interact to the user to produce readable symbolic results. Most analog integrated circuits (like opamps) can be analyzed in stages and simplified in stages. These are also common means for generating design equations. Currently we are working along these directions to enable automatic circuit reduction and design equation generation in AICE, which hopefully will lead to a groundbreaking sizing tool. So far too many papers have been pursuing simulation-driven approach to sizing, incapable of using design equations because no significant research has enabled the equation generation technology. It is time to consider approximate reasoning as a key means for design equation generation.

GPDD is a symbolic analysis method that generates symbolic results by processing the circuit topology rather than matrix. In fact, this has been the key enabling technology for AICE to generate reduced circuit automatically from a full-scale transistor-level circuit (Shi, Hu, and Deng, TODAES, 2017). Topological circuit reduction belongs to the regime of symbolic model order reduction (Shi, Hu, and Shi, TCAD, 2006). Recently, we have found that symbolic model reduction seems to be a critical technology to realize “approximate reasoning-based” automation for CMOS analog ICs.

Summary of AICE functionalities

Already implemented

• Design equation generation (including poles and zero for multi-stage circuits)
• Stage-form circuit reduction to facilitate design equation generation
• Symbolic distortion analysis (frequency dependent) for multi-stage models
• Symbolic CMRR analysis (frequency dependent) for differential cells
• SPICE simulation support
• Numerical evaluation and plotting
• TF (transfer function) generation
• Schematic editor

To be implemented

• Computer Algebra System (by integrating open source GiNaC)
• Sizing support
• Opamp circuit topology synthesis
• Cell-based transistor-level opamp schematic synthesis
• Other mixed-signal circuit extensions (switched-capacitor, sigma-delta modulator, etc.)

AICE Developer

AICE has been developed by the Mixed-Signal Design Automation (MSDA) Lab at Shanghai Jiao Tong University. Student currently in charge of the Web-AICE maintenance is Hao Limin (haolimin01@sjtu.edu.cn). If you have question or suggestions on this web tool, please feel free to contact him. The Web-AICE tool is a simplified version of our research tool AICE which is a piece of desktop software written in Qt. Web-AICE provides a web-based schematic interface; the analysis work is sent to a server maintained by our lab.

You are welcome to use AICE for learning, teaching, or research for free, if you publish your work, please acknowledge this tool in the following citation

References

1. Guoyong Shi, "Automatic stage-form circuit reduction for multistage opamp design equation generation," ACM Transactions on Design Automation of Electronic Systems, vol. 25, no. 1, October, 2019, pp. 2:1-26.
2. Guoyong Shi, "Symbolic distortion analysis of multistage amplifiers," IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 66, no. 1, January 2019, pp. 369-382.
3. Guoyong Shi, "Generating the closed-form second-order characteristics of analog differential cells by symbolic perturbation," IEEE Transactions on Circuits and Systems – I: Regular Papers, accepted for publication, vol. 65, no. 9, September 2018, pp. 2939-2950.
4. Guoyong Shi, “Toward automated reasoning for analog IC design by symbolic computation – A survey,” Integration, the VLSI Journal, 60 (2018), 117-131.
5. Guoyong Shi, Hanbin Hu, and Shuwen Deng, "Topological approach to automatic symbolic macromodel generation for analog ICs," ACM Transactions on Design Automation of Electronic Systems, vol. 22, no. 3, 2017, pp. 47:1-25.
6. Guoyong Shi, "Topological approach to symbolic pole-zero extraction incorporating design knowledge," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 11, 2017, pp. 1765-1778.
7. Hao Yu and Guoyong Shi, “Developing a web-based symbolic circuit analysis tool for learning and design aid,” Proc. 14th Int’l Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), June 2017, Taormina, Italy.
8. Yanjie Gu and Guoyong Shi, "An interactive program for automatic network function generation with insights", International Symposium on Circuits and Systems (ISCAS), May, 2015, Lisbon, Portugal, pp. 1810-1813.
9. Guoyong Shi, Sheldon X.-D. Tan, E. Tlelo-Cuautle, Advanced Symbolic Analysis for VLSI Systems - Methods and Applications, Springer Science + Business Media, New York, 2014. (ISBN 978-1-4939-1102-8).
10. Guoyong Shi, "Graph-Pair Decision Diagram Construction for Topological Symbolic Circuit Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 2, Feb. 2013, pp. 275-288.
11. Guoyong Shi, "A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits", Analog Integrated Circuits and Signal Processing, 74:331-343, 2013.
12. Guoyong Shi, B. Hu, and C.-J. R. Shi, "On symbolic model order reduction," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1257-1272, July 2006. (Donald O. Pederson Best Paper Award 2007)

Acknowledgement

The fundamental research on the AICE tool has been funded by Natural Science Foundation of China (NSFC) under the grants No. 60572028, 60876089, 61176129, 61474145 and 61974087 since 2006

Last updated: Jan. 21, 2022